13 semiconductor, inc. 7 8 9 10 11 12 13 14 15 16 17 description the epic ei88c681/EI68C681 duart dual universal asynchronous receiver and transmitter is a data com- munication device that provides two fully independent full duplex asynchronous communication channels in a single package. the duart is designed for use in microprocessor based systems and may be used in a polled or interrupt driven environment. two basic versions of the duart are available, each optimized for use with various microprocessor families: the 88c81 for 8085/85, 8080/88, z80, z8000, 68xx and 65xx family based systems., and the 68c681 for 68000 family based systems. a programmable mode of the ei88c681 versions provides an interrupt daisy chain for use in z80 and z8000 based systems. the bus inter- faces are however general enough to allow interfacing with other microprocessors and microcontrollers. the 88c681 and 68c681 are enhanced versions of the signetics 2681 and the motorola 68681, and are pin and function compatible with those devices. each channel of the duart may be independently programmed for operating mode and data format. the operating speed of each receiver and transmitter can beselected from baud rate generator, from the multi-purpose on chip counter/timer or from an external 1 x or 16 x clock. the bit rate generator can operate directly from a crystal connect- ed across two pins or from an external clock. the ability to independently program the operating speed of the receiv- er and transmitter of each channel makes the duart attractive for split-speed channel application such as clus- tered terminal systems. both receive and transmit data is quadruple-buffered in on-chip fifo to minimize the risk of receiver overrun or to reduce overhead in interrupt-drive applications. EI68C681 ei88c681 dual uart features ? full duplex, dual channel asynchronous receiver and transmitter ? quadruple-buffered receiver and transmitter ? stop bits programmable in 1/16-bit increments ? internal bit rate generator with 23 bit rates ? independent bit rate selection for each rx and tx ? maximum bit rate: 1 x clock - 2 mb/sec., 16 x clock- 250 kb/sec. ? normal, auto-echo, local loop-back and remote loop-back modes ? multi-function 16-bit counter/timer ? interrupt output with 8 maskable interrupt ing conditions ? interrupt vector output on acknowledge ? programmable interrupt daisy chain ? up to 15 i/o pins (depending on package and version) ? multidrop mode compatible with 8051 nine- bit mode ? on-chip oscillator for crystal ? stand-by mode to reduce operating power ? advanced cmos low power technology pin configuration 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a3 ip0 wr? rd? rxdb nc txdb op1 op3 op5 op7 ce? reset x2 x1/clk? rxda nc txda op0 op2 op4 op6 d1 d3 d5 d7 gnd nc intr d6 d4 d2 d0 a2 ip1 a2 ip3 a1 nc vcc ip4/iei ip5/ieo ip6/iack ip2 ei88c681 40 65432144434241 28 18 19 20 21 22 23 24 25 26 27 39 29 30 31 32 33 34 35 36 37 38 7 17 16 15 14 13 12 11 10 9 8 cs reset x2 x1/clk rxda nc txda op0 op2 op4 op6 a4 ip0 r/wn dtack rxdb nc txdb op1 op3 op5 op7 d1 d3 d5 d7 gnd nc intrn d6 d4 d2 d0 a3 ip1 a2 ip3 a1 nc vcc ip4 ip5 iackn ip2 EI68C681 44-pin plcc 44-pin plcc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a1 ip3 a2 ip1 a3 a4 ipo r/w? dtack? rxdb txdb op1 op3 op5 op7 d1 d3 d5 d7 gnd vcc ip4 ip5 iack? ip2 cs? reset? x2 x1/clk rxda txda op0 op2 op4 op6 d0 d2 d4 d6 intr? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 e i 6 8 c 6 8 1 40-pin dip 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a0 ip3 a1 ip1 a2 a3 ipo wrn rdn rxdb txdb op1 op3 op5 op7 d1 d3 d5 d7 gnd vcc ip4/iei ip5/ieo ip6/iackn ip2 cen reset x2 x1/clk rxda txda op0 op2 op4 op6 d0 d2 d4 d6 intrn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 e i 8 8 c 6 8 1 40-pin dip
14 semiconductor, inc. EI68C681 ei88c681 dual uart the duart provides a flow control capability to inhibit transmission from a remote device when the buffer of the receiving duart is full, thus preventing loss of data. the duart also provides a general purpose 16- bit counter/timer (which may also be used as a programmable bit rate generator), a multipurpose input port and a multipurpose output port. block diagram bus buffer 8 d0-d7 operation control address decode r/w control interrupt control imr isr ivr timing and control logic channel transmit logic receive logic txda rxda channel b (as above) txdb rxdb input port ipcr acr 6 4 8 ip0-ip6 output port opcr opr vcc gnd r/w? dtack? ce? a0-a3 reset? intr? iack? x1/clk x2 these ports can be used as general purpose i/o ports or can be assigned specific functions such as clock inputs or status/interrupt outputs under program control. the EI68C681 are fabricated using epics advanced cmos process to provide high performance and low power consumption.
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